1. Field of the Invention
The invention relates to a method of fabricating a flash memory, and more particularly to a method of fabricating a flash memory, which can increase layout design for circuit.
2. Description of the Related Art
Nonvolatile memory is currently applied to electronic devices to store structure data, program data and other data during repeated reading and writing episodes. The field of nonvolatile memory has recently focused on the electrically erasable programmable ROM (EEPROM) and EEPROM is broadly used for personal computer and electronic devices. Conventional EEPROM is accomplished by a floating gate transistor and has the advantages of writing, erasing and storing. However, EEPROM has the drawback of slow writing and reading speeds. The more recently developed flash memory EEPROM is already faster.
FIG. 1 is cross-sectional view of conventional flash memory, which mainly consists of a floating gate transistor. A tunneling oxide layer 102 is formed on a substrate 100 and a floating gate 104 is then formed thereon. Also, a control gate 108 is formed on the floating gate 104. A dielectric layer 106 is formed between the control gate 108 and the floating gate 104. N-type source/drain regions 110, 112 are formed on the sides of the floating gate 108 under the surface of the semiconductor substrate 100. An oxide spacer used to protect the floating gate transistor is formed on the sidewalls of the floating gate 104 and the control gate 108. As the data is stored, a high voltage of about 12V is added between drain region 110 and source region 112 while a high voltage is also applied on the control gate 108. Accordingly, hot electrons are discharged from the source region 112 and pass through the tunneling oxide layer 102 nearby the drain region 110. Finally, the hot electrons are injected and trapped in the floating gate 104 and they increase the threshold voltage of the floating gate transistor to achieve the object of data storage. On the other hand, as the data is erased, a proper negative voltage should be applied on the control gate 108 and the electrons trapped in the floating gate 108 can be passed through the tunneling oxide layer 105 and escape, resulting in erasing data. In this manner, the floating gate transistor can return to its pre-data storage state.